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AN714 vishay siliconix document number: 70585 08-jun-00 www.vishay.com faxback 408-970-5600 1 a compact controller for brushless dc motors wharton mcdaniel the drive electronics for 3-phase brushless dc motors often occupy a surprising amount of space. complex circuitry is needed to drive the power mosfets, and this gets even more complex in applications above 15 v. above 15 v, level shifted circuitry is required for proper drive of the high-side mosfets, whether they are n-channel or p-channel. add to this the possible need for heat sinks. even when the r ds(on) of the mosfets is low enough to eliminate the requirement for heatsinking, the mosfets' package size will require a lot of board area or headroom above the pc board surface. the si9979 brushless dc controller eliminates much of this complexity for applications in the 20- to 40-v dc range. housed in a 7-mm sqfp package, the si9979 reduces assembly cost and simplifies both motor and electronics packaging. the si9979 is a monolithic controller with integral high-side drive circuitry, allowing easy implementation of an all-n-channel three-phase bridge. the commutation logic has been configured to work with either 60 or 120 commutation sensor spacing. the internal voltage regulator allows the si9979 to operate over a wide input voltage range, 20 to 40 v dc, and to power the commutation sensors over this same range. control inputs include direction, quadrature select, pwm, and braking. a tachometer output is also featured. protection features include cross-conduction protection, current limiting, and undervoltage lockout. the fault output indicates when undervoltage, overcurrent, disable, or invalid sensor shutdown has occurred.

functionally the si9979 is made up of the commutation logic, the gate drive outputs, v dd regulator and output, and protection circuitry. figure 1. si9979 functional block diagram in a in c brk pwm tach qs v+ gt a f/r en v dd r t v dd input logic v dd v ref v ref v ref v dd v ref cap a cap b low-side u.v. lockout v ref + i s i s + r t /c t 42 43 2 4 5 6 10 9 11 8 18 17 34 20 19 low-voltage regulator high-side u.v. lockout bootstrap reg. charge pump s a 35 gt b 30 bootstrap reg. charge pump s b 31 cap a 36 cap b 32 gb a 33 gb b 29 v dd 13-16, 21-24 gnd cap c gt c 26 bootstrap reg. charge pump s c 27 cap c 28 gb c 25 one shot 37-41, 44-48 fault 7 in b v dd 3 60/120 v dd 1 v ref
AN714 vishay siliconix www.vishay.com faxback 408-970-5600 2 document number: 70585 08-jun-00
the commutation logic generates the basic commutation signals from the commutation sensors and modifies those signals according to the control inputs en, f/r , pwm, qs, and brk.
the basic commutation signals are generated from the code provided by the commutation sensors connected to in a , in b , and in c . these inputs are designed to be driven from open collector hall effect switches and have active pull ups to v dd . the 60/120 input must be set to be compatible with the sensor spacing used. it also has an active pull-up to v dd , with the default condition being 60-degree spacing. figure 1 gives the basic timing for both 60-degree and 120-degree commutation. the control inputs en, f/r , pwm, qs, and brk are ttl compatible inputs with internal pull-ups. ttl compatibility allows easy interface with microcontrollers and other common logic devices. functions are divided as follows: en input enables the outputs, f/r determines the direction of the motor's rotation, pwm accepts a digital pulse width modulation signal for controlling the motor's speed, qs determines whether bottom only or bottom and top mosfets are chopped by the pwm signal, and brk breaks the motor by turning on all the bottom mosfets. the default conditions are en - enabled, f/r - forward rotation, pwm - no chopping on active gate drives, qs - only bottom mosfets chopped by pwm, and brk - braking function on. this output is an extension of the commutation logic. when one of the commutation sensors changes state, a negative going pulse is emitted (500 ns typical). this gives six pulses per electrical revolution. the output is configured as an open drain for easy interfacing. each phase or half-bridge output is driven by a pair of n-channel mosfets. these are controlled by a low- and a high-side gate driver. they have been designed to drive a 600-pf load with a 110-ns rise time and a 50-ns fall time. the low-side gate is driven directly from the commutation logic and is powered by v dd . this means that v dd must be decoupled with a 1- f capacitor; otherwise the turn-on surge current can cause v dd to drop to the level of an undervoltage condition. figure 2. basic timing for both 60 and 120 commutation in a in b in c in a in b in c gt- a gt b gt c gb a gb b gb c phase a phase b phase c 60 spacing 120 spacing top gate drive bottom gate drive drive outputs
AN714 vishay siliconix document number: 70585 08-jun-00 www.vishay.com faxback 408-970-5600 3 the high side is a floating circuit powered from a combination bootstrap/charge pump supply. the bootstrap capacitor is charged to v dd when ever the low-side mosfet is turned on. for the rest of the time, the charge pump keeps the bootstrap capacitor charged, replacing the charge used in powering the high-side circuitry and in turning on the mosfet. the value of the bootstrap capacitor is a function of the mosfet being driven. the bootstrap voltage should not drop more than 1 v as the result of a mosfet turn-on. for a 60-v dual n-channel mosfet like the si4946ey, 30 nc (qg) is required for turn-on at a v gs of 10 v. using the equation c = qg/v gs , 3 nf is required to provide sufficient charge for turn-on. to meet the criteria of dropping only 1 v at turn-on, the capacitor needs to be 10 times as large, making the equation c boot = 10(qg/v gs ). this makes the minimum value of c boot equal to 0.03 f. table 1 gives minimum recommended values for several mosfets that might be used with the si9979. this minimum recommended value is one standard value above the minimum calculated value. part number r ds(on) qg @ v gs = 10 v (nc) minimum recommended c boot ( f) si4946 0.055 30 0.039 si9956 0.10 7 0.001
the regulation circuitry of the si9979 has been sized to source 20 ma to power the commutation sensors. when the operating ambient temperature rises to 70 c, the input voltage (v+) must be limited to 32 v dc. figure 3. external v dd regulator v dd si9979 v dd out v+ 1 f otherwise the si9979 may overheat. in cases where this condition cannot be met, or where more current is required, an external series pass npn can be added as shown in figure 3. the protection circuitry provides current limit, cross- conduction protection, undervoltage lockout, and the fault output. the current limit circuitry consists of a comparator driving a one-shot multivibrator (figure 4). the comparator has an internal 100-mv reference voltage on the inverting input and an external sensing resistor connected to the noninverting input. these inputs should be connected directly to the sensing resistor. this will eliminate the effects of any noise in the ground traces. the motor current must generate 100 mv across a sensing resistor for the comparator to trip. this in turn triggers the one-shot, turning off the active mosfets for a period defined by the product of rt and ct. if the current has dropped below the threshold by the time the off period has expired, the mosfets will be turned on again. if the overcurrent condition remains after the off period has expired, the mosfets will be held off until the current drops below the threshold. with the current limit off period in the 100- s range, cycle-by-cycle current limiting is achieved. if the current limit off period is reduced to the 10- s range, a constant current mode current limit is achieved. in this mode, the rms current (and therefore the torque) is maximized for the current limit setting. this is particularly useful when a maximum acceleration rate is required at power on. figure 5 shows typical current waveforms for durations of the off period. when driven in the anti-phase mode, the high-side and low-side mosfets of each active phase are toggled. to prevent shoot-through, each half-bridge has break-before- make circuitry. this delays the mosfet turn for 250 ns from the turn off of the opposite mosfet.
internal circuitry monitors the voltage level on v dd and the high-side supplies. this ensures that there is sufficient voltage to turn on the mosfets. should the voltage level on v dd drop below a nominal 12.2 v, all gate drives will be turned off until the undervoltage condition is gone. each of the high-side supplies is monitored only when it is referenced to ground. if the high-side voltage is under a nominal 12.7 v, the high-side will not be allowed to turn on. a negative going transition indicates that an undervoltage, current limit, or invalid sensor code condition exists. this output is configured as an open drain.
123 d 1 square d square a l l 1 l 2 b e pin 1 indicator c a 1 figure 6. 48-pin sqfp package AN714 vishay siliconix www.vishay.com faxback 408-970-5600 4 document number: 70585 08-jun-00 figure 4. current limit circuitry one shot c t r t 100 mv r sense to commutation logic current from 3-phase mosfet bridge figure 5. current waveforms 10 s 100 s
dim min max min max a 1.35 1.60 0.053 0.063 a 1 0.04 0.16 0.002 0.006 b 0.14 0.26 0.006 0.010 c 0.117 0.177 0.005 0.007 d 6.90 7.10 0.272 0.280 d 1 8.70 9.30 0.343 0.366 e 0.40 0.60 0.016 0.024 l 7.80 0.307 l 1 7.80 8.20 0.307 0.323 l 2 0.30 0.70 0.012 0.028 0 7 0 7 *for reference only the si9979 was packaged in a 48-pin sqfp to make drive circuits as compact as possible. the package has a 7-mm body with a total footprint of 9.3 mm on a side, occupying 86.5 mm 2 . the package dimensions are given in figure 6. beyond the basic footprint, the ground pins of the package should be connected to copper. this will help transfer heat out of the package and in to the pc board (figure 7). heat dissipation is especially important when the internal regulator is used to supply the current to the commutation sensors.
AN714 vishay siliconix document number: 70585 08-jun-00 www.vishay.com faxback 408-970-5600 5 figure 7. pad pattern with heat sinking copper (2 )
figure 8 shows a typical 3-phase brushless dc drive circuit. designers should consider both the motor being driven and any conditions imposed by the system when selecting the values of the current sense resistor, the r/c for the current limit one-shot, and the bootstrap capacitor, as well as the actual mosfets.

the motor being driven will be operated at 24 v dc. the typical load current is 2 a. the starting current must be limited to 5-a peak because of a system power supply limitation. it will take five seconds for the motor to accelerate the load to speed.

most brushless dc motors use hall effect switches with open collector outputs. these can be connected directly to in a , in b , and in c . however, there are some motors which use hall effect sensors with differential outputs. these are not compatible with the commutation inputs on the si9979. the circuit in figure 9 is an example of how differential output hall sensors can be interfaced to the single ended inputs of the si9979.
the current limit level is determined by the motor starting requirements, such as acceleration time, the power capability of the power mosfets, and the capability of the system power supply to supply current to the motor. for this design, the current limit level will be set at 5 a peak. there is a simple way to set this level. select a sensing resistor which will give 100 mv when 5 a flows through it. using ohm's law, rs = 100 mv/ipk. therefore a 20-m resistor is required. a 0.5-w resistor will handle the starting condition, since it is a transient condition. at the load current of 2 a, power dissipation is less than 0.10 w. 33 10 8 20 29 9 19 42 43 1 2 3 5 6 7 34 35 36 30 31 32 si9979cs v+ fault gnd q1 q4 q2 q5 q3 q6 17 26 27 28 25 tach pwm c 5 c 6 c 7 18 11 cap a cap c cap b v+ v dd in a in b in c en f/r qs brk fault s a gt a s b gt b s c gt c gb c gb b gb a i s i s + r t /c t tach r t gnd 12-16, 21-24 37-41, 44-48 (18-22, 27-30) figure 8. three-phase brushless dc motor controller 4 60/120 pwm r 2 c3 0.1 f c1 47 f c2 1 f r1 10 k c4 0.1 f c8 1 f c9 1 f c10 1 f d. gnd en f/r qs brk gnd hc hb ha v dd a b c
AN714 vishay siliconix www.vishay.com faxback 408-970-5600 6 document number: 70585 08-jun-00 figure 9. interface for differential hall sensors r1, 1 k r2, 1 k c1, 0.01 c5, 0.1 c4, 0.1 r7, 1.3 k r8, 1.3 k 1 2 3 4 v+ v ha ha+ hb ab+ hc hc+ v dd in a in b in c gnd c4, 0.1 to si9979 to differential halls r3, 1 k r4, 1 k c2, 0.01 5 6 r5, 1 k r6, 1 k c3, 0.01 7 8 there are alternative ways of setting current limits which use standard resistors to adjust the level. the first method is to use a resistive divider (figure 10). this forces the voltage drop across the sensing resistor to be greater than 100 mv, so 100 mv can be achieved at is+. if this method is used to get the 5-a level, r sense should be selected at 50 m . a current of 5 a will generate a 250-mv drop across rs. then select values for r1 and r2 to divide this by 2.5, applying 100 mv to is+. setting r1 to 4.2 k and r2 to 6.2 k provides this division. this adjustability is gained at the cost of increasing the power rating of the sensing resistor to 1.5 w. another way to get an adjustable current limit level is to bias the is- pin up from ground (figure 11). this raises the threshold from 100 mv to 100 mv + vbias. with the 50-m sense resistor, 150 mv of bias needs to be applied to is- to raise the threshold to the 250-mv level required for a 5-a current limit. the bias voltage must be kept under 0.8 v to ensure the input is not damaged. as in the resistive divider method, this method forces the increase in the sense resistor's power rating. also, the stability of the threshold voltage is affected by the stability of the bias voltage.

if the current limit off time is kept short, acceleration can take place as quickly as possible while respecting the peak starting current of 5 a. the rec ommended setting is 10 s. since this off time is defined by the product of r t and c t , r t is set to 10 k , making c t equal to 0.001 f. dc motors demand more current during startup than they do under normal running conditions. as a result, the most important specification for the power mosfets is their ability to withstand the starting current. this is especially true when surface-mount devices are involved. if the current starting level is 5 a, and the current limit circuitry is set for constant current operation, then power dissipation will determine the device chosen. the si4946ey little foot power mosfet is a good choice for this application. its worst case on resistance is 110 m . this puts the power dissipation at approximately 1.7 w. with the r ja of 68.5 c/w, the junction temperature will stay below 150 c in ambient temperatures as high as 45 c. figure 10. resistive divider adjustment of current limit level one shot c t r t 100 mv r sense to commutation logic current from 3-phase mosfet bridge r1 r2 figure 11. reference voltage offset adjustment of current limit level c t r t 100 mv r sense to commutation logic current from 3-phase mosfet bridge r1 0.8 v max one shot
AN714 vishay siliconix document number: 70585 08-jun-00 www.vishay.com faxback 408-970-5600 7 the value of the bootstrap capacitor is determined by the gate charge required for the mosfet selected. the si4946ey requires 30 nc (qg) at a v gs of 10 v (figure 12). using the equation c boot = 10 (qg/v gs ), the typical value is 0.03 f. table 1 shows a recommended minimum value of 0.039 f, which provides some headroom. figure 12. gate-to-source voltage (v) q g total gate charge (nc) v gs 10 05 8 6 4 2 0 10 15 20 25 30 v ds = 25 v i d = 2 a si9940 careful attention should be paid to decoupling, to routing of traces that carry the motor current, and to placement of the power mosfets. there are several decoupling capacitors in the design. the capacitors that are decoupling ic pins should be placed as close as possible to the pin itself, with the ground side of the capacitor going directly to an ic ground pin. decoupling of the power bus should occur at the mosfets to minimize the surge current in the traces. separate power and ground traces should be run to eliminate noise generated by fast mosfet transitions. these traces should be terminated as close as possible to the v+ and gnd inputs on the pc board. wherever separate traces are not feasible, the common trace should be as wide as possible. wide traces should be connected to the drain pins of the power mosfets to draw heat away from their packages. these traces should be at least 0.1o wide. figure 13 shows a sample pc board layout using the si9979 with si9940 mosfets. the overall dimensions of this board are 2.1o 1.85o. this size board can be mounted directly on a motor.

drive circuitry can be made more compact when high levels of integration are combined with surface-mount packaging. the pc board layout shown below is small enough to be mounted directly on a motor. this keeps the motor leads short and minimizes the switching noise associated with long motor leads. little foot mosfets help minimize the board area while allowing the designer to tailor the design to the motor being driven. combined with the si9979, the result is a compact, all-surface-mount solution allowing fully automated assembly. figure 13. a) component placement b) pc board layout

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